Samsung Unveils Memory Stacked Above AI Chips

Samsung Electronics has unveiled two new memory architectures designed for artificial intelligence computing, including a design that stacks high-bandwidth memory directly on top of AI accelerators rather than beside them.

The concept models, named zHBM and zNAND-O, were presented at the Future of Memory and Storage conference in Santa Clara, California, on 4 August.

What is zHBM?

Samsung said zHBM vertically stacks high-bandwidth memory directly above AI accelerators, moving beyond conventional designs in which the memory sits alongside the processor.

Shortening the distance data travels between processor and memory is intended to raise bandwidth and reduce power consumption. Both are limiting factors when running large AI models, where processors frequently sit idle waiting for data.

What did Samsung announce at FMS 2026?

At the Future of Memory and Storage conference in Santa Clara on 4 August 2026, Samsung Electronics presented concept models of two new memory architectures for artificial intelligence computing. The first, zHBM, stacks high-bandwidth memory vertically above AI accelerators rather than positioning it alongside the processor, which the company says will increase bandwidth and improve power efficiency. The second, zNAND-O, is a NAND solution built on Samsung V-NAND technology and aimed at real-time, data-intensive AI applications. Samsung also unveiled V10 BV-NAND, an architecture using wafer bonding to stack more than 400 layers, which the company states increases memory density by approximately 58 per cent over the previous V9 generation. Samsung competes with SK Hynix and Micron in a memory market approaching one trillion dollars in value.

What else was shown?

Samsung introduced V10 BV-NAND, built on a new bonding architecture. Applying wafer bonding to stack memory cells raised density by about 58 per cent over the previous generation, with more than 400 layers.

The announcement came thirteen years after the company introduced the first V-NAND technology at the 2013 Flash Memory Summit. Its wider roadmap covers HBM4E, HBM5 and LPDDR5X-PIM.

Why does this matter commercially?

Samsung is competing with SK Hynix, which established an early position in the AI memory boom, and with Micron in a market approaching a trillion dollars.

Announcing next-generation architecture ahead of rivals has become central to securing data centre contracts, because customers commit to memory roadmaps years before the hardware ships.

Shares in Samsung and SK Hynix have been volatile this week, both falling close to 9 per cent on Monday after a record rally the previous Friday.

The memory bottleneck

Processing power has grown faster than the ability to feed data to it. In large model training and inference, the constraint is often how quickly memory can supply the accelerator rather than how fast the accelerator can compute.

High-bandwidth memory addresses this by stacking memory dies and connecting them through a wide interface. Placing the stack directly above the processor, as zHBM proposes, shortens the path further.

Both zHBM and zNAND-O were presented as concept models rather than products with announced shipping dates.

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